1. Field of the Invention
The present invention generally relates to data processing and, more particularly, to a data processing apparatus and a data processing method using a ring bus.
2. Description of the Related Art
Conventionally, to rapidly and efficiently realize a series of data processing such as print image processing, there is a known method in which entire data processing is divided into predetermined functions and configured as hardware. Then, the respective hardware modules are connected in a processing flow order, and the series of data processing is executed in a pipeline manner.
On the other hand, in image processing, processing can be efficiently realized by changing an order of a series of processing. For example, when an image is output to an output apparatus having a predetermined pixel number, to match the number of pixels (resolution), the resolution needs to be converted. If the input image has a larger number of pixels than the pixel number of the output apparatus, the resolution is converted on an upstream side of the processing. Although it is better to perform the processing after reducing the number of pixels, if the input image has a smaller number of pixels than the pixel number of the output apparatus, processing may be performed in a low pixel number state without converting the resolution, and it is better to convert the resolution immediately before output (downstream side).
Further, processing is also performed to convert from a predetermined space (e.g., input device space) into a standard space (e.g., 600 ppi resolution, CIELAB color space etc.). When the space is converted into a separate space (e.g., output device space), the processing order executed by a space conversion unit on an input side and an output side (order of processing such as one-dimensional look up table (LUT), matrix calculation, three-dimensional LUT etc.) is reversed. More specifically, if the processing order can be changed, the same processing module can be shared by the input side and the output side. However, in the above described data processing method, the processing order cannot be changed. Therefore, in a case like that described above, measures such as mounting an unnecessary module (i.e., a plurality of modules having the same functions) are taken, for example.
To solve the above problem, Japanese Patent Nos. 2522952 and 2518293 each discuss a method for connecting each processing module in a ring network. According to these methods, the processing order can be changed by changing a connection destination of the data on the ring network. Further, in the technique discussed in Japanese Patent No. 2518293, each of the processing modules is executed by respective processors. Therefore, the processing order can also be changed by changing the program of the respective processors.
However, on the ring networks discussed in Japanese Patents No. 2522952 and No. 2518293, compared with an output rate of a certain module, the processing of a module which receives data from the certain module is slow. When an input rate is relatively low, the module which receives the data cannot receive all pieces of the data. Consequently, slots for storing valid packets on the ring bus are occupied by the data pieces which are not received by the module. In other words, a phenomenon (deadlock) occurs in which data cannot be output to the ring bus. Once a deadlock occurs in the ring bus, it is necessary to discard all of the packets on the ring bus, initialize all of the modules, and then restrict the output (or suppress the input rate) of the module that was the cause of the deadlock. Thus, there is a problem that if there is a plurality of data paths formed on the ring bus, it is sometimes necessary to redo the processing even for a valid data path (a data path does not use the module that was the cause of the deadlock).